The present invention relates to a semiconductor device and a method for manufacturing a semiconductor memory device and, more specifically, to a DRAM (dynamic random access memory) adopting a self-aligned contact structure.
Recently, in semiconductor memories (semiconductor memory devices) such as a DRAM, a self-aligned contact structure has been adopted more frequently in accordance with a reduction of design rules.
FIG. 1 schematically shows the structure of a prior art DRAM.
The DRAM includes a memory cell section 100a and a peripheral circuit section 100b containing a core circuit section. These sections 100a and 100b are provided on the same semiconductor substrate 101.
In the memory cell section 100a, an element isolating insulation film 102 is formed selectively in a surface area of the semiconductor substrate 101, and an element region is delimited by an element isolation region. A plurality of gate electrodes 105a (three gate electrodes in this prior art case) are each provided on the element region with a gate insulation film 103a interposed therebetween. The top surface of each of the gate electrodes 105a is covered with an insulation film 104a and the sides thereof are protected thereby.
An interlayer insulation film 106 is provided almost all over the resultant structure so as to fill a space between adjacent gate electrodes 105a. A bit-line contact 107a is formed in the interlayer insulation film 106, and one of source and drain diffusion regions 108a is connected to a bit line 109a through the bit-line contact 107a.
An interlayer insulation film 110 is formed on the bit line 109a, and a stacked capacitor including a storage electrode 111, an insulation film 112 and a plate electrode 113 is formed on the film 110. The storage electrode 111 is connected to the other of source and drain diffusion regions 108a' through a plug portion 114.
In the peripheral circuit section 100b, an element isolating insulation film 102 is formed selectively in a surface area of the semiconductor substrate 101, and an element region is delimited by an element isolation region. A gate electrode 105a is provided on the element region with a gate insulation film 103b interposed therebetween. The top surface of the gate electrode 105a is covered with an insulation film 104b and the sides thereof are protected thereby.
Further, in the element isolation region, an on-field gate electrode 105c is provided on the element isolating insulation film 102 with a gate insulation film 103c interposed therebetween. The top surface of the gate electrode 105c is covered with an insulation film 104c and the sides thereof are protected thereby.
The interlayer insulation film 106 is provided almost all over the resultant structure so as to fill a space between the gate electrodes 105b and 105c. An active contact 107b is formed in the interlayer insulation film 106, and one of source and drain diffusion regions 108b is connected to a wiring 109b having the same level as that of the bit line 109a through the active contact 107b.
A gate contact 107c is formed in the interlayer insulation film 106 and insulation film 104c, and the on-field gate electrode 105c is connected to a wiring 109c having the same level as that of the bit line 109 through the gate contact 107c.
In the DRAM so constituted, the bit-line contact 107a in the memory cell section 100a is formed in self-alignment with the gate electrodes 105a and usually filled with polysilicon which is advantageous to filling of a very small hole (a so-called self-aligned contact structure).
Since, in contrast, the peripheral circuit section 100b necessitates a low-resistance contact, metal such as tungsten is generally employed to fill the active contact 107b and gate contact 107c.
According to the self-aligned contact structure, the gate electrodes 105a are covered with the insulation films 104a such as SiN, and the films 104a stop etching to form a very small contact while keeping insulating properties between the bit-line contact 107a and gate electrodes 105a.
However, the foregoing prior art DRAM adopting the self-aligned contact structure has the problem that the bit-line contact 107a and active contract 107b connected to the semiconductor substrate 101 (properly speaking, connected to the source and drain diffusion layers 108a and 108b) and the gate contact 107c formed on the on-field gate electrode 105c, cannot be formed simultaneously using a single mask.
FIGS. 2A to 2F schematically show a process of manufacturing the prior art DRAM described above.
First, as illustrated in FIG. 2A, element isolating insulation films 102 are formed selectively in surface areas of a semiconductor substrate 101 to delimit element regions in a memory cell section 100a and a peripheral circuit section 100b. In the memory cell section 100a, gate electrodes 105a are each formed on the element region with a gate insulation film 103a interposed therebetween. The top surface of each of the gate electrodes 105a is covered with an insulation film 104a and the sides thereof are protected thereby. In the peripheral circuit section 100b, a gate electrode 105b is formed on the element region with a gate insulation film 103b interposed therebetween, and the top surface of the gate electrode 105b is covered with an insulation film 104b and the sides thereof are protected thereby.
Simultaneously, an on-field gate electrode 105c is formed on the element isolating insulation film 102 in the peripheral circuit section 100b with a gate insulation film 103c interposed therebetween., The top surface of the on-field gate electrode 105c is covered with an insulation film 104c and the sides thereof are protected thereby.
After that, impurities are ion-implanted into the surface areas of the semiconductor substrate 101 to form source and drain diffusion layers 108a and 108a' in the memory cell section 10a and source and drain diffusion layers 108b and 108b' in the peripheral circuit section 100b.
Then, as illustrated in FIG. 2B, an interlayer insulation film 106 is formed thick almost all over the semiconductor substrate 101 so as to fill a space between adjacent gate electrodes 105a, 105b and 105c. The top surface of the interlayer insulation film 106 is flattened by CMP (chemical mechanical polishing) or the like.
As shown in FIG. 2C, a resist pattern (first mask) 121 is formed on the interlayer insulation film 106. Using this resist pattern as a mask, the interlayer insulation film 106 is etched to form a contact hole 122, which reaches one of the source and drain diffusion regions 108a, in self-alignment with the gate electrodes 105a.
In FIG. 2D, the resist pattern 121 is removed and then conductive materials (e.g., polysilicon) are buried into only the contact hole 122 to form a bit-line contact 107a in the memory cell section 100a.
A resist pattern (second mask) 123 is formed on the interlayer insulation film 106. Using this pattern as a mask, the interlayer insulation film 106 is etched to form a contact hole 124, which reaches one of the source and drain diffusion regions 108b, in self-alignment with the gate electrode 105b.
Next, as illustrated in FIG. 2E, the resist pattern 123 is removed and then metal (e.g., tungsten) is buried into only the contact hole 124 to form an active contact 107b in the peripheral circuit section 100b.
A resist pattern (third mask) 125 is formed on the interlayer insulation film 106. Using this pattern, the interlayer insulation film 106 and insulation film 104c are etched to form a contact hole 126 which reaches the on-field gate electrode 105c.
Referring to FIG. 2F, the resist pattern 125 is removed and then metal (e.g., tungsten) is buried into only the contact hole 126 to form a gate contact 107c on the on-field gate electrode 105c.
A tungsten wiring is patterned on the interlayer insulation film 106 to form a bit line 109a connected to the bit-line contact 107a of the memory cell section 100a, a wiring 109b connected to the active contact 107b of the peripheral circuit section 100b, and a wiring 109c connected to the gate contact 107c on the on-field gate electrode 105c.
After that, in the memory cell section 100a, an interlayer insulation film 110 is formed, and a plug portion 114, which is connected to the other of the source and drain diffusion layers 108a', is formed through the interlayer insulation films 110 and 106. A storage electrode 111, a capacitor insulation film 112 and a plate electrode 113 are formed in the surface area of the interlayer insulation film 110 to constitute a stacked capacitor communicating with the plug portion 114. The DRAM having the structure shown in FIG. 1 is thus obtained.
As described above, in the prior art DRAM, the insulation film 104c on the on-field gate electrode 105c has to be eliminated at the same time when the contact hole 126 is made in order to form the gate contact 107c on the electrode 105c. For this reason, both the formation of the contact hole 126 and that of the contact holes 122 and 124 cannot be performed at the same time, the contact holes 122 and 124 being made by the self-aligned contact technique in which the insulation films 104a and 104b stop etching to form a contact.
Assume that, when the contact holes 124 and 126 are formed simultaneously using a single mask, a mask misalignment is caused to shift the opening position of the contact hole 124 toward the gate electrode 105b. In this case, the insulation film 104b covering the gate electrode 105b will also be etched in accordance with the mask misalignment.
When the insulation film 104b is so etched that the gate electrode 105b is exposed because of excessive mask misalignment, no contact-to-gate insulating properties can be maintained and accordingly the gate electrode 105b and active contact 107b are short-circuited with each other.
Especially, in a DRAM having a storage capacitor of about 1GB, a distance between a gate electrode and a contact formed on one of source and drain diffusion layers in the peripheral circuit section is about 0.1 .mu.m. The mask misalignment in a direction approaching the gate electrode makes the distance much smaller.
In manufacturing such a prior art DRAM, the gate contact 107c of the peripheral circuit section 100b, the bit-line contact 107a of the memory cell section 100a, or the active contact 107b of the peripheral circuit section 100b cannot be formed at once, and at least two types of masks are required to form a contact below the first-layered wiring layer. Consequently, the prior art DRAM has the drawbacks that not only the number of manufacturing steps is increased but also a yield against a short circuit between the wiring layer and contact is difficult to improve.